ADCs are used in a variety of electrical systems to convert electrical analog signals 3 into electrical digital signals. One type of ADC that is often used in electrical systems is called a full flash ADC. Another type of ADC that is often used in electrical systems is called a two-step ADC. In a full flash ADC, many comparators arranged in parallel with one another simultaneously receive the input analog voltage signal and the same clock signal. All bit decisions are made simultaneously based on the outputs of the comparators. In order to obtain high bit resolution at high speed, however, the comparators must be extremely fast. The use of such a large number of comparators results in a large amount of area and a large amount of power being consumed by the flash ADC. In addition, paralleling the large number of comparators results in high input capacitance, which limits the overall conversion speed of the full flash ADC.
Two-step ADCs use fewer comparators than full flash ADCs. In order to reduce the amount of area consumed by the ADC, a logical configuration is used that performs a combination of parallel and series conversions. The first step of the conversion process is a coarse conversion process that decides the values of the more significant bits of the multi-bit number that will ultimately be used to digitally represent the analog input voltage signal. The second step of the conversion process is a fine conversion process that decides the values of the less significant bits of the multi-bit number that will ultimately be used to digitally represent the analog input voltage signal. During the fine conversion process, the bits decided by the coarse conversion process are used to perform sub-ranging operations on either the input signal or the reference input signal to the fine conversion process. The fine conversion process then decides the values of the bits of less significance using either the sub-ranged input signal or the sub-ranged reference signal, or both The more significant bits decided by the coarse conversion process and the less significant bits decided by the fine conversion process are then combined to produce the ADC multi-bit output signal.
The two-step conversion process performed by the two-step ADC requires more time than the full conversion process performed by the flash ADC due to the fact that not all bit decisions are made in parallel, i.e., simultaneously, in the two-step ADC. An advantage of two-step ADCs is that they employ fewer comparators than the number of comparators employed in full flash ADCs. Consequently, two-step ADCs typically consume less power and require less chip area than full flash ADCs. For this reason, two-step ADCs are often preferred over full-flash ADCs.
FIG. 1 illustrates a block diagram of a known two-step ADC 2. The ADC 2 comprises a sampler 3, a CADC circuit 4, and FADC circuit 5, a sub-range multiplexer (MUX) 6, and an encoder 7. The sampler 3 receives an analog input voltage signal, ADC_IN, and a clock signal, ADC_CLK. The sampler 3 includes sampling circuitry (e.g., an n-type MOS switch) that samples ADC_IN on the rising edge of ADC_CLK and produces a signal sample value on the falling edge of ADC_CLK. The sampling process performed by the sampler 3 is typically referred to as Track and Hold (T/H) sampling.
The signal sample value that is output from the sampler 3 is received by the CADC circuit 4 and by the FADC circuit 5. However, the CADC circuit 4 processes the signal sample value before the FADC circuit 5 processes the signal sample value. The CADC circuit 4 processes the signal sample value output from the sampler 3 and decides the values of the more significant bits of the multi-bit signal that will ultimately be used to represent ADC_IN in digital format. The bit decisions produced by the CADC circuit 4 are used by the sub-ranging MUX 6 to either sub-range the value of signals that are input to the comparators (not shown) of the FADC circuit 4 or to sub-range the value of the reference signal that is used by the comparators of the FADC circuit 4. The FADC circuit 4 decides the values of the less significant bits of the multi-bit signal that will ultimately be used to represent ADC_IN in digital format. The encoder 7 combines the bit decisions produced by the FADC circuit 5 with the bit decisions produced by the CADC circuit 4 to obtain the final multi-bit number that is output from the ADC 2, ADC_Out.
In general, the disadvantage of two-step ADCs compared to full flash ADCs is the need for a clocking scheme in two-step ADCs that assigns different clock signal phases for use in the T/H sampling, the T/H buffer settling, the CADC conversion, the sub-ranging MUX conversion, and the FADC conversion. For the traditional two-step sub-ranging ADC shown in FIG. 1, a simple open loop buffer arrangement is used for the sampling operations performed in the sampler 3. The use of the open loop buffer arrangement results in a total settling time window of only ½tCLK being available for T/H buffer settling, CADC conversion, sub-ranging conversion, and FADC conversion, where tCLK is equal to one clock period of ADC_CLK. The use of a closed loop T/H amplifier instead of an open loop buffer in the sampler 3 would essentially double this settling time window by allowing the sampler 3 to obtain the next sample value without affecting the conversion process being performed in the FADC circuit 4. However, for similar bandwidth and driving capability, a two-step ADC that uses a closed loop T/H amplifier generally consumes significantly more power and chip area than that consumed by a two-step ADC that uses an open loop buffer.
FIG. 2 illustrates a block diagram of another typical two-step sub-ranging ADC 12. The ADC 12 shown in FIG. 2 is similar to the ADC 2 shown in FIG. 1 except that the ADC 12 uses two FADC circuits 15A and 15B and two sub-ranging MUXes 16A and 16B. The FADC circuits 15A and 15B are often referred to as being “interleaved”. The use of the two FADC circuits 15A and 15B results in a settling time window, TW, of ½tCLK for each of the CADC conversion process, the MUX sub-ranging conversion process, and the FADC conversion process, where tCLK is the length of time of one clock cycle of clock signal ADC_CLK. In other words, the use of the two interleaved FADC circuits 15A and 15B provides a total settling time window, TWTOTAL, of 1.5tCLK for all of the CDAC, MUX sub-ranging and FADC conversion processes to complete. Similarly, two CADC circuits, or two CADC circuits plus two FADC circuits (not shown), can also be interleaved to obtain a similar improvement in the total settling time window.
The tradeoffs of using two FADC circuits or two CADC circuits to increase the settling time window are that more chip area and power are consumed by the comparators (not shown) of the sampler 3 due to the increased load created by the additional FADC or CADC circuits. Another tradeoff is that when multiple CADC or FADC circuits are used, there is an increase in the number of sources of potential bit decision mismatches in the CADC circuits or the FADC circuits, respectively.
A need exists for a two-step ADC that is capable of achieving an increased settling time window without increasing the amount of chip area and power that are consumed by the ADC and without increasing the number of sources of potential bit decision mismatches.